An integrated circuit (“IC”) is a device (e.g., a semiconductor device) that includes many electronic components, such as transistors, resistors, diodes, etc. These components are often interconnected to form multiple circuit components, such as gates, cells, memory units, arithmetic units, controllers, decoders, etc. An IC includes multiple layers of signal wiring that interconnect its electronic and circuit components. Traditionally, IC's use preferred direction (“PD”) wiring models, which specify a preferred wiring direction for each of their wiring layers. In preferred direction wiring models, the preferred direction typically alternates between successive wiring layers.
One example of a PD wiring model is the PD Manhattan wiring model, which specifies alternating layers of preferred-direction horizontal and vertical wiring. Another example of a PD wiring model is the PD diagonal wiring model, which specifies alternating layers of preferred-direction diagonal wiring. The PD diagonal wiring model can allow for shorter wiring distances than the PD Manhattan wiring model and can decrease the total wirelength needed to interconnect the electronic and circuit components of an IC. The PD diagonal wiring model is described in detail in U.S. patent application Ser. No. 10/334,690, filed Dec. 31, 2002, entitled “Method and Apparatus for Routing,” incorporated herein by reference and in U.S. patent application Ser. No. 10/013,819, filed Dec. 7, 2001, entitled “Routing Method and Apparatus That Use Diagonal Routes,” incorporated herein by reference
Design engineers design IC's by transforming logical or circuit descriptions of the IC's into geometric descriptions, called layouts. IC layouts typically include (1) circuit modules (i.e., geometric representations of electronic or circuit IC components) with signal pins, and (2) interconnect lines (i.e., geometric representations of signal wiring) that connect the signal pins of the circuit modules. A signal net is typically defined as a collection of signal pins that need to be connected.
To create layouts, design engineers typically use electronic design automation (“EDA”) applications. These applications provide sets of computer-based tools for creating, editing, and analyzing IC design layouts. One EDA tool is a signal wire router that defines routes for interconnect lines that connect the signal pins of signal nets. Signal wire routing is generally divided into two phases: global signal routing and detailed signal routing. For each signal net, global signal routing generates a “loose” route for the interconnect lines that are to connect the signal pins of the signal net. The “looseness” of a global signal route depends on the particular global signal router used. After global signal routes have been created, the detailed signal routing creates specific individual routes for each signal net. A signal wire router that consistently explores diagonal routing directions (referred to herein as a diagonal wire router) is described in the aforementioned patent application titled “Method and Apparatus for Routing.”
Each IC also contains a power grid structure that provides power and ground to each electronic and circuit component of an IC. Each electronic or circuit IC component has a power pin and a ground pin that is connected to the power grid structure. A power net is typically defined as a collection of power pins that need to be connected and a ground net is typically defined as a collection of ground pins that need to be connected.
Power grid structure components include stripes, rails, and vias which must be of a certain strength (i.e., size) to meet design constraints (i.e., minimum specifications that the power grid structure must meet in order to be acceptable for use in the IC). Power grid components, however, compete with signal wiring for area on an IC layer since they take up area on the IC layer that signal wiring could otherwise occupy. Also, power grid structure components can cause substantial blockage of signal wiring paths, especially on layers with the PD diagonal wiring model.
FIG. 1 illustrates a top view of a region of an IC layout having a conventional power grid structure 100. The power grid structure 100 includes stripes 105, rails 110, and vias 115. Stripes 105 are typically positioned vertically (i.e., parallel to the layout's y-coordinate axis) across an upper layer of the IC and provide power and ground to the IC. A stripe 105 that carries power is referred to as a power stripe 105 and a stripe 105 that carries ground is referred to as a ground stripe 105.
Rails 110 are typically positioned horizontally (i.e., parallel to the layout's x-coordinate axis) across at least one lower layer of the IC. Each rail 110 is connected to a stripe 105 through vias 115. A rail 110 connected to a power stripe 105 is referred to as a power rail 110 and a rail 110 connected to a ground stripe 105 is referred to as a ground rail 110.
Vias 115 are positioned perpendicular to the IC's layers (i.e., parallel to the layout's z-coordinate axis) and distribute power or ground from the stripes 105 to the rails 110. Multiple vias 115 are arranged in a via array which is used to connect a stripe 105 to a rail 110. For illustrative purposes, FIG. 1 shows a top view of a via array as enclosed by a rectangular bounding box, the via array being comprised of multiple vias 115. A via array has an area that is typically determined by an intersection area of a stripe 105 and rail 110 (i.e., locations where stripes 105 and rails 110 cross in terms of the layout's x and y-coordinate axes). The area of a via array is typically the same on each layer.
A via 115 (or via array) that connects a power stripe 105 to a power rail 110 is referred to as a power via 115 (or power via array) and a via 115 that connects a ground stripe 105 to a ground rail 110 is referred to as a ground via 115 (or ground via array). A power via 115 is typically located at every intersection of a power stripe 105 and power rail 110 and a ground via 115 is typically located at every intersection of a ground stripe 105 and ground rail 110.
Since the vias 115 of the power grid structure are positioned upright through the IC, they can cause blocking of the signal wiring needed to interconnect the electronic and circuit components of the IC. The amount of wiring blockage varies from layer to layer depending on the PD wiring model of the layer. As shown in FIG. 1, diagonal direction arrows 130 illustrate how diagonal wiring paths are blocked by vias 115 of the conventional power grid structure 100.
Conventionally, design engineers manually define the power grid structure by methods of trial and error. For example, designer engineers typically estimate stripe width and stripe spacing values (the distance from one stripe to the next) based on prior experience. The stripe width effects the area of a via array since the area of a via array is typically determined by an intersection area of a stripe and rail. The estimated stripe width (and resulting via array area) is typically larger than needed to meet design constraints for the power grid structure so that the stripes and vias of the power grid structure take up more area than necessary on an IC layer. Also, the estimated stripe spacing values effect the locations of the via arrays since a via array is placed at stripe and rail intersections. The estimated stripe spacing values typically place the via arrays in a position that causes a substantial amount of diagonal wiring blockage on layers with the PD diagonal wiring model.
Therefore, conventional power grid structures typically occupy more area on IC layers than necessary and cause substantial diagonal wiring blockage on layers with the PD diagonal wiring model. This is due to the fact that, conventionally, power grid components are not defined in a systematic way to minimize the area of the power grid structure or to minimize diagonal wiring blockage. Therefore, there is a need for an automated method and apparatus for defining a power grid structure that minimizes the area of the power grid structure and minimizes the diagonal wiring blockage caused by the power grid structure while still meeting the design constraints for the power grid structure.